--RSCFQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY RSCFQ IS
  PORT(R:IN STD_LOGIC;
       S:IN STD_LOGIC;
       Q:BUFFER STD_LOGIC;
       NQ:BUFFER STD_LOGIC);
END ENTITY RSCFQ;

ARCHITECTURE ART OF RSCFQ IS 
  COMPONENT MYNAND IS 
    PORT(A:IN STD_LOGIC;
         B:IN STD_LOGIC;
         C:OUT STD_LOGIC);
  END COMPONENT MYNAND;
BEGIN
  U1:MYNAND PORT MAP(A=>S,B=>NQ,C=>Q);
  U2:MYNAND PORT MAP(A=>Q,B=>R,C=>NQ);
END ARCHITECTURE ART;

CONFIGURATION CFG OF RSCFQ IS
  FOR ART
    FOR U1,U2:MYNAND
      USE ENTITY WORK.MYNAND(ART1);
    END FOR;
  END FOR;
END CONFIGURATION CFG;
